high-speed multi-frequency pll clock buff er roboclockii? junio r cy7b9930 v cy7b9940 v cypress semiconductor corporation ? 3901 north first street san jose , ca 95134 408-943-2600 document #: 38-07271 rev. *b revised july 25, 2002 features 12?100 mhz (cy7b9930v), or 24?200 mhz (cy7b9940v) input/output operation matched pair output skew < 200 ps zero input-to-output delay 10 lvttl 50% duty-cycle outputs capable of driving 50 terminated lines commercial temp. range with eight outputs at 200 mhz industrial temp. range with eight outputs at 200 mhz 3.3v lvttl/lv differential (lvpecl), fault-tolerant and hot insertable reference inputs multiply ratios of (1?6, 8, 10, 12) operation up to 12x input frequency individual output bank disable for aggressive power management and emi reduction output high-impedance option for testing purposes fully integrated pll with lock indicator low cycle-to-cycle jitter (<100 ps peak-peak) single 3.3v 10% supply 44-pin tqfp package functional description the cy7b9930v and cy7b9940v high-speed multi- frequency pll clock buffers offer user-selectable control over system clock functions. this multiple-output clock driver provides the system integrator with functions necessary to optimize the timing of high-performance computer or commu- nication systems. ten configurable outputs can each drive terminated trans- mission lines with impedances as low as 50 ? while delivering minimal and specified output skews at lvttl levels. the outputs are arranged in three banks. the fb feedback bank consists of two outputs, which allows divide-by functionality from 1 to 12. any one of these ten outputs can be connected to the feedback input as well as driving other inputs. selectable reference input is a fault tolerance feature that allows smooth change over to secondary clock source, when the primary clock source is not in operation. the reference inputs are configurable to accommodate both lvttl or differ- ential (lvpecl) inputs. the completely integrated pll reduces jitter and simplifies board layout. 3 3 3 3 fs output_mode fbds0 fbds1 dis2 dis1 qfa0 qfa1 2qa0 2qa1 2qb0 2qb1 1qa0 1qa1 1qb0 1qb1 lock fbka refa+ refa? refb+ refb? refsel divide phase freq. detector filter vco control logic divide generator feedback bank bank 2 bank 1 matrix 1 3 2 36 35 34 37 38 39 40 41 42 43 44 25 24 23 26 27 28 33 31 32 30 29 vccq refa+ refa ? refsel refb? refb+ dis1 gnd dis2 vccq fs gnd 2qb1 vccn 2qb0 gnd gnd gnd vccn gnd 2qa0 2qa1 9 10 11 8 7 6 4 5 lock fbds1 fbds0 gnd qfa0 vccn vccq gnd fbka gnd qfa1 20 21 22 1qb1 vccn output_mode gnd 1qb0 gnd gnd 1qa1 vccn 1qa0 gnd 19 18 17 16 15 14 13 12 cy7b9930v/40v 44-pin tqfp pin configuration functional block diagram [+] feedback [+] feedback
roboclockii? junio r cy7b9930 v cy7b9940 v document #: 38-07271 rev. *b page 2 of 9 block diagram description phase frequency detector and filter these two blocks accept signals from the ref inputs (refa+, refa?, refb+ or refb?) and the fb input (fbka). correction information is then generated to control the frequency of the voltage controlled oscillator (vco). these two blocks, along with the vco, form a phase-locked loop (pll) that tracks the incoming ref signal. the roboclock ii ? junior has a flexible ref input scheme. these inputs allow the use of either differential lvpecl or single-ended lvttl inputs. to configure as single-ended lvttl inputs, the complementary pin must be left open (inter- nally pulled to 1.5v), then the other input pin can be used as a lvttl input. the ref inputs are also tolerant to hot insertion. the ref inputs can be changed dynamically. when changing from one reference input to the other reference input of the same frequency, the pll is optimized to ensure that the clock outputs period will not be less than the calculated system budget (t min = t ref (nominal reference clock period) ? t ccj (cycle-to-cycle jitter) ? t pdev (max. period deviation)) while reacquiring lock. vco, control logic, and divide generator the vco accepts analog control inputs from the pll filter block. the fs control pin setting determines the nominal operational frequency range of the divide by one output (f nom ) of the device. f nom is directly related to the vco frequency. there are two versions of the roboclock ii junior, a low-speed device (cy7b9930v) where f nom ranges from 12 mhz to 100 mhz, and a high-speed device (cy7b9940v) which ranges from 24 mhz to 200 mhz. the fs setting for each device is shown in table 1 . the f nom frequency is seen on ?divide-by-one? outputs. note: 1. for all three-state inputs, high indicates a connection to v cc , low indicates a connection to gnd, and mid indicates an open connection. internal termination circuitry holds an unconnected input to v cc /2. 2. the level to be set on fs is determined by the ?nominal? operating frequency (f nom ) of the v co . f nom always appears on an output when the output is operating in the undivided mode. the ref and fb are at f nom when the output connected to fb is undivided. 3. the maximum output frequency is 200 mhz. pin definitions [1] name i/o type description fbka input lvttl feedback input . refa+, refa? refb+, refb? input lvttl/ lvdiff reference inputs : these inputs can operate as differential pecl or single-ended ttl reference inputs to the pll. when operating as a single-ended lvttl input, the comple- mentary input must be left open. refsel input lvttl reference select input : the refsel input controls how the reference input is configured. when low, it will use the refa pair as the reference input. when high, it will use the refb pair as the reference input. this input has an internal pull-down. fs input 3-level input frequency select : this input must be set according to the nominal frequency (f nom ). see table 1 . fbds[0:1] input 3-level input feedback divider function select . these inputs determine the function of the qfa0 and qfa1 outputs. see table 2 . dis[1:2] input lvttl output disable : each input controls the state of the respective output bank. when high, the output bank is disabled to the ?hold-off? or ?hi-z? state; the disable state is deter- mined by output_mode. when low, the [1:4]q[a:b][0:1] is enabled. see table 3 . these inputs each have an internal pull-down. lock output lvttl pll lock indicator : when high, this output indicates the internal pll is locked to the reference signal. when low, the pll is attempting to acquire lock. output_mode input 3-level input output mode : this pin determines the clock outputs? disable state. when this input is high, the clock outputs will disable to high-impedance (hi-z). when this input is low, the clock outputs will disable to ?hold-off? mode. when in mid, the device will enter factory test mode. qfa[0:1] output lvttl clock feedback output : this pair of clock outputs is intended to be connected to the fb input. these outputs have numerous divide options. the function is determined by the setting of the fbds[0:1] pins. [1:2]q[a:b][0:1] output lvttl clock output . vccn pwr output buffer power : power supply for each output pair. vccq pwr internal power : power supply for the internal circuitry. gnd pwr device ground . table 1. frequency range select fs [2] cy7b9930v cy7b9940v f nom (mhz) f nom (mhz) min. max. min. max. low12262452 mid 24 52 48 100 high 48 100 96 200 [3] [+] feedback [+] feedback
roboclockii? junio r cy7b9930 v cy7b9940 v document #: 38-07271 rev. *b page 3 of 9 divide matrix the divide matrix is comprised of three independent banks: two banks of clock outputs and one bank for feedback. each clock output bank has two pairs of low-skew, high-fanout output buffers ([1:2]q[a:b][0:1]), and an output disable (dis[1:2]). the feedback bank has one pair of low-skew, high-fanout output buffers (qfa[0:1]). one of these outputs may connect to the selected feedback input (fbka+). this feedback bank also has two divider function selects fbds[0:1]. the divide capabilities for each bank are shown in table 2. output disable description the outputs of bank 1 and bank 2 can be independently put into a hold-off or high-impedance state. the combination of the output_mode and dis[1:2] inputs determines the clock outputs? state for each bank. when the dis[1:2] is low, the outputs of the corresponding bank will be enabled. when the dis[1:2] is high, the outputs for that bank will be disabled to a high-impedance (hi-z) or hold-off state depending on the output_mode input. table 3 defines the disabled output functions. the hold-off state is intended to be a power saving feature. an output bank is disabled to the hold-off state in a maximum of six output clock cycles from the time when the disable input (dis[1:2]) is high. when disabled to the hold-off state, outputs are driven to a logic low state on its falling edge. this ensures the output clocks are stopped without glitch. when a bank of outputs is disabled to hi-z state, the respective bank of outputs will go hi-z immediately. lock detect output description the lock detect output indicates the lock condition of the integrated pll. lock detection is accomplished by comparing the phase difference between the reference and feedback inputs. phase error is declared when the phase difference between the two inputs is greater than the specified device propagation delay limit (t pd ). when in the locked state, after four or more consecutive feedback clock cycles with phase-errors, the lock output will be forced low to indicate out-of-lock state. when in the out-of-lock state, 32 consecutive phase-errorless feedback clock cycles are required to allow the lock output to indicate lock condition (lock = high). if the feedback clock is removed after lock has gone high, a ?watchdog? circuit is implemented to indicate the out-of-lock condition after a time-out period by deasserting lock low. this time out period is based upon a divided down reference clock. this assumes that there is activity on the selected ref input. if there is no activity on the selected ref input then the lock detect pin may not accurately reflect the state of the internal pll. factory test mode description the device will enter factory test mode when the output_mode is driven to mid. in factory test mode, the device will operate with its internal pll disconnected; input level supplied to the reference input will be used in place of the pll output. in test mode the selected fb input must be tied low. all functions of the device are still operational in factory test mode except the internal pll and output bank disables. the output_mode input is designed to be a static input. dynamically toggling this input from low to high may tempo- rarily cause the device to go into factory test mode (when passing through the mid state). factory test reset when in factory test mode (output_mode = mid), the device can be reset to a deterministic state by driving the dis2 input high. when the dis2 input is driven high in factory test mode, all clock outputs will go to hi-z; after the selected reference clock pin has 5 positive transitions, all the internal finite state machines (fsm) will be set to a deterministic state. the deterministic state of the state machines will depend on the configurations of the divide selects and frequency select input. all clock outputs will stay in high-impedance mode and all fsms will stay in the deterministic state until dis2 is deasserted. when dis2 is deasserted (with output_mode still at mid), the device will re-enter factory test mode. table 2. output divider function function selects output divider function fbds1 fbds0 bank1 bank2 feedback bank low low /1 /1 /1 low mid /1 /1 /2 low high /1 /1 /3 mid low /1 /1 /4 mid mid /1 /1 /5 mid high /1 /1 /6 high low /1 /1 /8 high mid /1 /1 /10 high high /1 /1 /12 table 3. dis[1:2] pin functionality output_mode dis[1:2]/fbdis output mode high/low low enabled high high hi-z low high hold-off mid x factory test [+] feedback [+] feedback
roboclockii? junio r cy7b9930 v cy7b9940 v document #: 38-07271 rev. *b page 4 of 9 absolute maximum conditions (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature .....................................? 40 c to +125 c ambient temperature with power applied ..? 40 c to +125 c supply voltage to ground potential .................? 0.5v to +4.6v dc input voltage ..........................................? 0.3v to v cc +0.5v output current into outputs (low) .............................40 ma static discharge voltage............................................ >2000v (per mil-std-883, method 3015) latch-up current.................................................... >200 ma operating range range ambient temperature v cc commercial 0 c to +70 c 3.3v 10% industrial ?40 c to +85 c 3.3v 10% electrical characteristics over the operating range parameter description test conditions min. max. unit lvttl compatible output pins (qfa[0:1], [1:4]q[a:b][0:1], lock) v oh lvttl high voltage qfa[0:1], [1:2]q[a:b][0:1] v cc = min., i oh = ?30 ma 2.4 ?v lock i oh = ?2 ma, v cc = min. 2.4 ? v v ol lvttl low voltage qfa[0:1], [1:2]q[a:b][0:1] v cc = min., i ol = 30 ma ? 0.5 v lock i ol = 2 ma, v cc = min. ? 0.5 v i oz high-impedance state leakage current ?100 100 a lvttl compatible input pins (fbka, refa, refb, refsel, dis[1:2]) v ih lvttl input high fbka+, ref[a:b] min. < v cc < max. 2.0 v cc +0.3 v refsel, dis[1:2] 2.0 v cc +0.3 v v il lvttl input low fbka+, ref[a:b] min. < v cc < max. ?0.3 0.8 v refsel, dis[1:2] ?0.3 0.8 v i i lvttl v in >v cc fbka+, ref[a:b] v cc = gnd, v in = 3.63v ? 100 a i lh lvttl input high current fbka+, ref[a:b] v cc = max., v in = v cc ?500 a refsel, dis[1:2] v in = v cc ?500 a i ll lvttl input low current fbka+, ref[a:b] v cc = max., v in = gnd ?500 ? a refsel, dis[1:2] ?500 ? a 3-level input pins (fbds[0:1], fs, output_mode) v ihh three level input high [4] min. < v cc < max. 0.87*v cc ?v v imm three level input mid [4] min. < v cc < max. 0.47*v cc 0.53*v cc v v ill three level input low [4] min. < v cc < max. 0.13*v cc v i ihh three level input high current 3-level input pins v in = v cc ?200 a i imm three level input mid current 3-level input pins v in = v cc /2 ?50 50 a i ill three level input low current 3-level input pins v in = gnd ?200 ? a lvdiff input pins (ref[a:b]) v diff input differential voltage 400 v cc mv v ihhp highest input high voltage 1.0 v cc v v illp lowest input low voltage gnd v cc ? 0.4 v v com common mode range (crossing voltage) 0.8 v cc v note: 4. these inputs are normally wired to v cc , gnd, or left unconnected (actual threshold voltages vary as a percentage of v cc ). internal termination resistors hold the unconnected inputs at v cc /2. if these inputs are switched, the function and timing of the outputs may glitch and the pll may require an additional t lock time before all data sheet limits are achieved. [+] feedback [+] feedback
roboclockii? junio r cy7b9930 v cy7b9940 v document #: 38-07271 rev. *b page 5 of 9 operating current i cci internal operating current cy7b9930v v cc = max., f max [5] ?200ma cy7b9940v ? 200 ma i ccn output current dissipation/pair [6] cy7b9930v v cc = max., c load = 25 pf, r load = 50 ? at v cc /2, f max ?40ma cy7b9940v ? 50 ma capacitance parameter description test conditions min. max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v ? 5 pf switching characteristics over the operating range [7, 8, 9, 10, 11] parameter description cy7b9930/40v-2 cy7b9930/40v-5 unit min. max. min. max. f in clock input frequency cy7b9930v 12 100 12 100 mhz cy7b9940v 24 200 24 200 mhz f out clock output frequency cy7b9930v 12 100 12 100 mhz cy7b9940v 24 200 24 200 mhz t skewpr matched-pair skew [12, 13] ?185?185ps t skewbnk intrabank skew [12, 13] ?200?250ps t skew0 output-output skew (same frequency and phase, rise to rise, fall to fall) [12, 13] ?250?550ps t skew1 output-output skew (same frequency and phase, other banks at different frequency, rise to rise, fall to fall) [12, 13] ?250?650ps t ccj1-3 cycle-to-cycle jitter (divide by 1 output frequency, fb = divide by 1, 2, 3) ?150?150ps peak- peak t ccj4-12 cycle-to-cycle jitter (divide by 1 output frequency, fb = divide by 4, 5, 6, 8, 10, 12) ?100?100ps peak- peak t pd propagation delay, ref to fb rise ?250 250 ?500 500 ps t pddelta propagation delay difference between two devices [14] ?200 200ps t refpwh ref input (pulse width high) [15] 2.0 ? 2.0 ? ns t refpwl ref input (pulse width low) [15] 2.0 ? 2.0 ? ns t r /t f output rise/fall time [16] 0.15 2.0 0.15 2.0 ns t lock pll lock time from power-up ? 10 ? 10 ms t relock1 pll re-lock time (from same frequency, different phase) with stable power supply ?500?500 s notes: 5. i cci measurement is performed with bank1 and fb bank configured to run at maximum frequency (f nom = 100 mhz for cy7b9930v, f nom = 200 mhz for cy7b9940v), and all other clock output banks to run at half the maximum frequency. fs and output_mode are asserted to the high state. 6. this is dependent upon frequency and number of outputs of a bank being loaded. the value indicates maximum i ccn at maximum frequency and maximum load of 25 pf terminated to 50 ? at v cc /2. 7. this is for non-three level inputs. 8. assumes 25 pf max. load capacitance up to 185 mhz. at 200 mhz the max load is 10 pf. 9. both outputs of pair must be terminated, even if only one is being used. 10. each package must be properly decoupled. 11. ac parameters are measured at 1.5v, unless otherwise indicated. 12. test load c l = 25 pf, terminated to v cc /2 with 50 ? . 13. skew is defined as the time between the earliest and the latest output transition among all outputs for which the same phase delay has been selected when all outputs are loaded with 25 pf and properly terminated up to 185 mhz. at 200 mhz the max load is 10 pf. 14. guaranteed by statistical correlation. tested initially and after any design or process changes that may affect these parame ters. 15. tested initially and after any design or process changes that may affect these parameters. 16. rise and fall times are measured between 2.0v and 0.8v. electrical characteristics over the operating range (continued) parameter description test conditions min. max. unit [+] feedback [+] feedback
roboclockii? junio r cy7b9930 v cy7b9940 v document #: 38-07271 rev. *b page 6 of 9 t relock2 pll re-lock time (from different frequency, different phase) with stable power supply [17] ?1000?1000 s t odcv output duty cycle deviation from 50% [11] ?1.0 1.0 ?1.0 1.0 ns t pwh output high time deviation from 50% [18] ?1.5?1.5ns t pwl output low time deviation from 50% [18] ?2.0?2.0ns t pdev period deviation when changing from reference to reference [19] ? 0.025 ? 0.025 ui t oaz dis[1:2] high to output high-impedance from active [12, 20] 1.0 10 1.0 10 ns t oza dis[1:2] low to output active from output is high-impedance [20, 21] 0.5 14 0.5 14 ns ac test loads and waveform [22] notes: 17. f nom must be within the frequency range defined by the same fs state. 18. t pwh is measured at 2.0v. t pwl is measured at 0.8v. 19. ui = unit interval. examples: 1 ui is a full period. 0.1 ui is 10% of period. 20. measured at 0.5v deviation from starting voltage. 21. for t oza minimum, c l = 0 pf. for t oza maximum, c l = 25 pf to 18 mhz, 10 pf from 185 to 200 mhz. 22. these figures are for illustration only. the actual ate loads may vary. switching characteristics over the operating range [7, 8, 9, 10, 11] (continued) parameter description cy7b9930/40v-2 cy7b9930/40v-5 unit min. max. min. max. 2.0v 0.8v 3.3v gnd 2.0v 0.8v 3.3v output (a) lvttl ac test load < 1ns < 1 ns (b) ttl input test waveform r1 r2 c l r1 = 910 ? r2 = 910 ? c l <30pf (includes fixture and probe capacitance) r1 = 100 ? r2 = 100 ? c l < 25 pf up to 185 mhz for lock output only for all other outputs 10 pf from 185 to 200 mhz [+] feedback [+] feedback
roboclockii? junio r cy7b9930 v cy7b9940 v document #: 38-07271 rev. *b page 7 of 9 ac timing diagrams [11] t pwl t pwh ref fb q t refpwh t refpwl t pd t ccj1-3,4-12 [1:4]q[a:b]0 [1:4]q[a:b]1 t skewpr [1:4]qa[0:1] [1:4]qb[0:1] t skewbnk t skewpr t skewbnk q other q t skew0,1 t skew0,1 2.0v 0.8v qfa0 or qfa1 or t odcv t odcv ref to device 1 and 2 fb device1 fb device2 t pd t pdelta t pdelta ordering information propagation delay (ps) max. speed (mhz) ordering code package name package type operating range 500 100 CY7B9930V-5AC a44 44-lead thin quad flat pack commercial 500 100 cy7b9930v-5ai a44 44-lead thin quad flat pack industrial 500 200 cy7b9940v-5ac a44 44-lead thin quad flat pack commercial 500 200 cy7b9940v-5ai a44 44-lead thin quad flat pack industrial 250 100 cy7b9930v-2ac a44 44-lead thin quad flat pack commercial 250 200 cy7b9940v-2ac a44 44-lead thin quad flat pack 250 100 cy7b9930v-2ai a44 44-lead thin quad flat pack industrial 250 200 cy7b9940v-2ai a44 44-lead thin quad flat pack [+] feedback [+] feedback
roboclockii? junio r cy7b9930 v cy7b9940 v document #: 38-07271 rev. *b page 8 of 9 ? cypress semiconductor corporation, 2003. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semi conductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies th at the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. roboclockii is a trademark of cypress semiconductor. all product and company names mentioned in this document are the trademarks of their respective holders. package diagrams 44-lead thin plastic quad flat pack a44 51-85064-*b [+] feedback [+] feedback
roboclockii? junio r cy7b9930 v cy7b9940 v document #: 38-07271 rev. *b page 9 of 9 document history page document title: cy7b9930v/cy7b9940v roboclockii? junior high-speed multi-frequency pll clock buffer document number: 38-07271 rev. ecn no. issue date orig. of change description of change ** 110536 12/02/01 szv change from spec number: 38-01141 *a 115109 7/03/02 hwt add 44tqfp package for both cy7b9930/40v ? industrial operating range *b 128463 7/29/03 rgl added clock input frequency (f in ) specifications in the switching character- istics table. added min. values for the clock output frequency (f out ) in the switching characteristics table. [+] feedback [+] feedback
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